发明授权
- 专利标题： Semiconductor device geometrical pattern correction process and geometrical pattern extraction process
- 专利标题（中）： 半导体器件几何图案校正过程和几何图案提取过程
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申请号： US09348316申请日： 1999-07-07
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公开(公告)号： US06183920B2公开(公告)日： 2001-02-06
- 发明人: Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
- 申请人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
- 优先权： JP10-192888 19980708
- 主分类号： G03F900
- IPC分类号： G03F900
摘要：
A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
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