An EEPROM device has memory cells each including of a memory transistor and a selection transistor. The memory transistor has a floating gate between a control gate and a conducting channel formed between a drain and a source. The selection transistor has its source connected to the drain of the memory transistor. During writing of data, the control gate of the memory transistor is grounded, the source of the memory transistor is kept in an open state, and a voltage corresponding to the data to be written in is applied to the gate and the drain of the selection transistor.