发明授权
US06195740B1 Constant reconstructing processor that execute an instruction using an operand divided between instructions
失效
使用在指令之间划分的操作数来执行指令的恒定重构处理器
- 专利标题： Constant reconstructing processor that execute an instruction using an operand divided between instructions
- 专利标题（中）： 使用在指令之间划分的操作数来执行指令的恒定重构处理器
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申请号： US09124659申请日： 1998-07-29
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公开(公告)号： US06195740B1公开(公告)日： 2001-02-27
- 发明人: Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
- 申请人： Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
- 优先权： JP9-204125 19970730
- 主分类号： G06F930
- IPC分类号： G06F930
摘要：
A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.
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