Defects in memory circuit (100) are efficiently corrected by selectively blowing fuses in a first plurality of fuses to describe a cell location of a defective cell within any of several memory array portions (110). Fuses in a second plurality of fuses are blown to describe indicate the particular memory array portion (112) containing the defective memory cell. During operation of the memory circuit (100), the cell location is forwarded to the memory array portion (112) containing the defective memory cell and a redundant memory cell (206) is used for data storage at the memory array portion (112) having a defective memory cell.