A circuit which uses less memory to store halftone arrays in a high addressability printer by storing regular halftone arrays as low addressability arrays and by outputting each pixel a number of times, the number being the ratio of high to low addressability. For example, if a high addressability system uses 4 sub pixels for each pixel, then one value of each low addressability array is stored in one location and the halftone circuit is controlled to output that value 4 times, once for each sub pixel thus saving memory by a factor of 4.