A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361. When the decoding unit 20 finds that the instruction includes a branch operation, the execution unit 30 executes the branch operation using the constant stored in the branching constant register 362. When the decoding unit 20 finds that the instruction includes an arithmetic operation, the execution unit 30 executes the arithmetic operation using the constant stored in the operation constant register 361.