发明授权
- 专利标题： Integrated circuit and method
- 专利标题（中）： 集成电路及方法
-
申请号： US09392988申请日： 1999-09-09
-
公开(公告)号： US06211035B1公开(公告)日： 2001-04-03
- 发明人: Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
- 申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
- 主分类号： H01L2120
- IPC分类号： H01L2120
摘要：
A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
信息查询
