The motion vector decoder includes a parameter delay block which delays transmissions of various input signals necessary for motion vector decoding; a motion vector residual block which extracts a motion residual value and outputs a positive number of the motion residual value; a motion vector code table block which searches for a motion code, a condition of a sign of the motion code, and a zero condition of the motion code using a variable length decoding table and outputting the searched values; a motion vector delta block which calculates a difference of motion vectors from the motion vector residual block and the motion vector code table block; a MV adder which adds the difference value received from the motion vector delta block and a motion vector of a preceding macroblock to output a new motion vector; and a register which updates a flip-flop corresponding to a current (r, s, t) of a new motion vector. The circuit blocks each have at least one flip-flop to allow processing of each block within a single clock.