发明授权
- 专利标题: Method of fabricating a semiconductor structure
- 专利标题(中): 制造半导体结构的方法
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申请号: US09435839申请日: 1999-11-08
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公开(公告)号: US06218287B1公开(公告)日: 2001-04-17
- 发明人: Akira Matsumoto
- 申请人: Akira Matsumoto
- 优先权: JP10-316546 19981106
- 主分类号: H01L214763
- IPC分类号: H01L214763
摘要:
On a substrate is provided a layered structure of a lower insulating layer, a lower etch stop layer, an upper insulating layer and an upper etch stop layer. A via hole is formed in a location above a doped region of the substrate, the via hole extending through the upper etch stop layer and the upper insulating layer to the lower etch stop layer. On the upper etch stop layer is placed a photoresist layer having a trench pattern to produce a replica of the trench pattern, followed by removal of any of the photoresist layer. A portion of the upper insulating layer is then removed through the replica of the trench pattern to form a wire trench and a portion of the lower insulating layer is removed through the removed portion of the lower etch stop layer so that the via hole is extended to the doped region. The upper etch stop layer is removed and a portion of the lower etch stop layer is removed simultaneously through the wire trench. Finally, metal is then deposited in the via hole and the wire trench.
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