发明授权
- 专利标题: Configuration memory architecture for FPGA
- 专利标题(中): FPGA配置存储器架构
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申请号: US09030616申请日: 1998-02-25
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公开(公告)号: US06222757B1公开(公告)日: 2001-04-24
- 发明人: Prasad Rau , Atul V. Ghia , Suresh M. Menon
- 申请人: Prasad Rau , Atul V. Ghia , Suresh M. Menon
- 主分类号: G11C1100
- IPC分类号: G11C1100
摘要:
A configuration memory architecture for an FPGA that eliminates the need for a regular array of word lines and bit lines is disclosed. The memory is comprised, in the preferred embodiment, of a plurality of memory bytes. Each memory byte has eight SRAM latches, a single flip flop and a one-of-eight decoder having a data input coupled to the inverting output of the flip flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The decoder also has address and write control inputs which are coupled to a state machine or other programmable device that controls the sequencing of the loading operation to load configuration data into the memory. The flip flops of all the memory bytes are coupled together in a serpentine shift register. Loading of configuration data involves shutting all paths through the decoder down, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path in each memory byte from the output of the flip flop to the data input of the selected SRAM latch. The process is then repeated for all other SRAM latches.