发明授权
- 专利标题: Computer system having an interrupt handler
- 专利标题(中): 具有中断处理程序的计算机系统
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申请号: US09219790申请日: 1998-12-23
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公开(公告)号: US06223246B1公开(公告)日: 2001-04-24
- 发明人: Hironobu Miyamoto
- 申请人: Hironobu Miyamoto
- 优先权: JP9-355391 19971224
- 主分类号: G06F1324
- IPC分类号: G06F1324
摘要:
Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether or no the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern n the interrupt activation condition flag storing unit. As a result of the determination, an interrupt process is performed in accordance with an operational description storing unit which stores a process corresponding to the flag pattern if the pattern exits. Thereafter, bit for the flag corresponding to the executed process is cleared out.
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