A method of forming an interconnect, comprising the following steps. A dielectric layer, having an upper surface, is formed over a semiconductor structure. A trench, having side walls and a bottom, is formed within the dielectric layer. A barrier layer is then formed over the dielectric layer and lining the trench's side walls and bottom. A first copper layer is deposited on the barrier layer, filling the lined trench and blanket filling the barrier layer covered dielectric layer. The first copper layer is planarized, exposing the upper surface of the dielectric layer and forming a dished copper filled trench. A second copper layer is selectively deposited on the dished copper filled trench by either electroless plating or chemical vapor deposition (CVD). The second copper layer extending above the upper surface of the dielectric layer. The second copper layer is then planarized to form an essentially planar copper filled trench, or interconnect, level with the upper surface of said dielectric layer.