An integrated circuit is presented. The integrated circuit may include a memory cell formed above an insulating base. The insulating base may either be arranged above a substrate or serve as a substrate itself. A transistor may be arranged above the memory cell. The transistor is preferably dielectrically isolated from the memory cell. In a preferred embodiment, a segmented substrate is arranged between the memory cell and transistor. The segmented substrate preferably includes a first conductive substrate layer arranged above and dielectrically spaced from the memory cell. A second conductive substrate layer may be formed above the first conductive substrate layer. The transistor may be arranged upon and within the second conductive substrate layer. Preferably, the segmented substrate further includes an intersubstrate dielectric layer interposed between the second conductive substrate layer and the first conductive substrate layer. The intersubstrate dielectric layer preferably serves to insulate the first conductive substrate layer from the second conductive substrate layer. An integrated circuit so configured may be fabricated with greater device density at reduced cost.