The data output circuit in a clock synchronous DRAM comprises a first data transfer circuit to which the data read from a memory is input and which transfers the input data to the output side in synchronization with an internal clock, an equalizing circuit to which the output of the first data transfer circuit is input during a read operation by a burst operation and to which high-impedance data is input after the read operation, a second data transfer circuit connected to the equalizing circuit, and an output buffer to which the output of the second data transfer circuit is input. The second data transfer circuit transfers all the data to the output buffer in synchronization with an output clock. This eliminates the dependence of the data access time and data hold time on data item and/or cycle and facilitates the timing control of the output control signal.