发明授权
- 专利标题: Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
- 专利标题(中): 处理器使用较少的硬件和指令转换设备减少指令类型的数量
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申请号: US09144298申请日: 1998-08-31
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公开(公告)号: US06230258B1公开(公告)日: 2001-05-08
- 发明人: Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
- 申请人: Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
- 优先权: JP9-234354 19970829; JP10-095645 19980408
- 主分类号: G06F930
- IPC分类号: G06F930
摘要:
An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.
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