发明授权
US06232797B1 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities
有权
具有数据缓冲器控制电路的集成电路器件，其中考虑到时钟不规则
- 专利标题： Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities
- 专利标题（中）： 具有数据缓冲器控制电路的集成电路器件，其中考虑到时钟不规则
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申请号： US09378099申请日： 1999-08-20
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公开(公告)号： US06232797B1公开(公告)日： 2001-05-15
- 发明人: Won-jae Choi , Jung-bae Lee , Si-yeol Lee
- 申请人： Won-jae Choi , Jung-bae Lee , Si-yeol Lee
- 优先权： KR98-35854 19980901
- 主分类号： H03K1900
- IPC分类号： H03K1900
摘要：
Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in an active logic state and disabled to block passage of data from the data input to the data output when the control signal is in an inactive logic state. A data buffer control circuit is also provided. The data buffer control circuit latches a latency signal in response to a control clock, generates the control signal from the latched latency signal and comprises a pulse generator that drives the control signal to its inactive logic state in-sync with an edge of the latency signal. This inactive control signal can be used to disable the data buffer.