A modulation encoder includes a base conversion circuit that converts a partitioned input data stream from a first base representation in accordance with the size of groups of bits in the partitioned stream into a second base representation. The base conversion circuit includes a circuit to produce intermediate values of the partitioned stream in the second base representation and a residual value logic circuit that performs modulo-arithmetic on intermediate values modulo the second base representation, and a one's complement logic network fed by the residual value logic to produce output code words. A modulation decoder includes a one's complement logic circuit fed by modulation code words to produces residual value words; and a base conversion circuit that converts residual value words from a first base representation into a second base representation to provide original user data.