发明授权
- 专利标题: Optimal write conductors layout for improved performance in MRAM
- 专利标题(中): 最佳写导体布局,以提高MRAM的性能
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申请号: US09624134申请日: 2000-07-21
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公开(公告)号: US06236590B1公开(公告)日: 2001-05-22
- 发明人: Manoj Bhattacharyya , Thomas Anthony
- 申请人: Manoj Bhattacharyya , Thomas Anthony
- 主分类号: G11C1115
- IPC分类号: G11C1115
摘要:
An optimal write conductor layout structure for improved MRAM performance is disclosed. A write conductor layout structure for a magnetic memory cell includes a data storage layer having a first layer width in a first direction and a second layer width in a second direction. The data storage layer is positioned between a first conductor having a first width in the first direction and a second conductor having a second width in the second direction. The first and second conductors cross the data storage layer in the first and second directions respectively. The first width of the first conductor is less than the first layer width of the data storage layer and the first width of the first conductor is positioned so that the first layer width overlaps the entirety of the first width of the first conductor. The second width of the second conductor is less than the second layer width of the data storage layer and the second width of the second conductor is positioned so that the second layer width overlaps the entirety of the second width of the second conductor. The narrow widths of the first and second conductors eliminates misalignment between the conductors and the data storage layer, reduces leakage of a write magnetic field generated by currents applied to the first and second conductors, and can generate the write magnetic field with less current thereby reducing power consumption in the memory cell.
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