A hole filling process for an integrated circuit in which two wiring levels in the integrated circuit are connected by a narrow hole, especially where the underlying level is silicon. First, a physical vapor deposition (PVD) process fills a barrier tri-layer into the hole. The barrier tri-layer includes sequential layers of Ti, TiN, and graded TiNx, grown under conditions of a high-density plasma. Thereafter, a first aluminum layer is PVD deposited under conditions of a high-density plasma. A filling aluminum layer is then deposited by standard PVD techniques.