A pair of synchronized clock sources provides phase and frequency synchronous first and second clocks accompanied by first and second control signals to a clock selection circuit having a data selector comprising a first synchronizer and a second synchronizer which re-times the first and second control signals, and these re-timed outputs that are coupled to an asynchronous state machine. The asynchronous state machine changes state by logically operating on the re-timed control signals in conjunction with a state bit. This state bit is used to control the multiplexer, which achieves glitch-free switching between the first clock source and the second clock source.