发明授权
US06240017B1 Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device 有权
降低栅极氧化物和跨越可擦除存储器件的高电压晶体管内的结的电压应力

  • 专利标题: Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
  • 专利标题(中): 降低栅极氧化物和跨越可擦除存储器件的高电压晶体管内的结的电压应力
  • 申请号: US09353267
    申请日: 1999-07-14
  • 公开(公告)号: US06240017B1
    公开(公告)日: 2001-05-29
  • 发明人: Binh Quang LePauling Chen
  • 申请人: Binh Quang LePauling Chen
  • 主分类号: G11C1604
  • IPC分类号: G11C1604
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
摘要:
The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The microcontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.
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