A processor-based transmitter-receiver system and method in which a receiver receives coded signals from at least two transmitters. A circuit for receiving a first coded signal from a first transmitter and a second coded signal from a second transmitter. Each of the coded signals includes a unique identification code and a variable security code. A memory stores at least two codes, each including a unique identification code and a variable security code. A processor coupled to the circuit and the memory, compares each of the received coded signals with each of the stored sets of codes. The processor generates a valid signal if one of the received coded signals matches one of the stored codes.