发明授权
US06245662B1 Method of producing an interconnect structure for an integrated circuit 失效
制造用于集成电路的互连结构的方法

  • 专利标题: Method of producing an interconnect structure for an integrated circuit
  • 专利标题(中): 制造用于集成电路的互连结构的方法
  • 申请号: US09122080
    申请日: 1998-07-23
  • 公开(公告)号: US06245662B1
    公开(公告)日: 2001-06-12
  • 发明人: Mehul NaikSamuel Broydo
  • 申请人: Mehul NaikSamuel Broydo
  • 主分类号: H01L214763
  • IPC分类号: H01L214763
Method of producing an interconnect structure for an integrated circuit
摘要:
A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.
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