发明授权
US06246118B1 Low dielectric semiconductor device with rigid, conductively lined interconnection system
有权
具有刚性,导电衬里互连系统的低介电半导体器件
- 专利标题: Low dielectric semiconductor device with rigid, conductively lined interconnection system
- 专利标题(中): 具有刚性,导电衬里互连系统的低介电半导体器件
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申请号: US09252185申请日: 1999-02-18
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公开(公告)号: US06246118B1公开(公告)日: 2001-06-12
- 发明人: Matthew S. Buynoski
- 申请人: Matthew S. Buynoski
- 主分类号: H01L2348
- IPC分类号: H01L2348
摘要:
Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid, conductive lining, such as, a hard metal, e.g., W, Mo, Os, Ir or alloys thereof. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating the hard metal to line the interconnection system and forming dielectric protective layers, e.g., a silane derived oxide bottommost protective layer, on the uppermost metallization level.