Silicon oxide layers are provided in a substrate. That part of the silicon oxide layer which is located in a memory cell section MC has a thickness. That part of the silicon oxide layer which is located in a peripheral circuit section PC has a thickness, which is less than the thickness. The memory cell section MC has transistors, each having a source region and a drain region which contact the silicon oxide layer. The peripheral circuit section PC has transistors, each having a source region and a drain region which are spaced apart from the silicon oxide layer. The transistors of the peripheral circuit section PC are provided in well regions. A back-gate bias is applied to the transistors of the peripheral circuit section PC through impurity layers.