发明授权
US06252567B1 Multi-output digital to analog converter 失效
多输出数模转换器

  • 专利标题: Multi-output digital to analog converter
  • 专利标题(中): 多输出数模转换器
  • 申请号: US09291429
    申请日: 1999-04-13
  • 公开(公告)号: US06252567B1
    公开(公告)日: 2001-06-26
  • 发明人: Franciscus P. M. Budzelaar
  • 申请人: Franciscus P. M. Budzelaar
  • 优先权: EP98201197 19980415
  • 主分类号: G09G320
  • IPC分类号: G09G320
Multi-output digital to analog converter
摘要:
In a multiple-output digital to analog converter, digital input data (Dd) is converted into a plurality of analog output voltages (Voi) across associated loads (Li). A timing generator (TG) generates time periods (Ti1) in dependence on the digital input data (Dd). A buffer (B1) has an output (O1) to supply a waveform (WF1) to the loads (Li) via a coupling circuit (S1i). The coupling circuit (S1i) couples a certain load (Li) to the buffer output (B1) during an associated time period (Ti1). The output voltage (Voi) across the certain load (Li) is related to a value of the waveform (Wf1) at the end of the associated time period (Ti1) when the coupling circuit decouples the load (Li) from the buffer output (O1). The multiple-output digital to analog converter further comprises a plurality of dummy loads (Ldi), each one of the dummy loads (Ldi) is associated to a corresponding one of the loads (Li). The dummy loads (Ldi) are coupled to the buffer output (O1) when the corresponding load (Ldi) is decoupled from the buffer output (O1). A pre-setting circuit (B2, S2i) generates the voltages (Vdi) across the dummy loads (Ldi) so as to be substantially equal to the output voltages (Voi) across the associated loads (Li) occurring when the coupling circuit (S1i) decouples the load (Li) from the output buffer (B1).
信息查询
0/0