The present invention is directed to a sigma-delta D-A converter (300) with N stages, in which the nth stage, where n=1, 2, 3 . . . N, comprises a first adder (10) which adds a use signal x(k) (12) with an error signal errn(k−1) to an input signal en(k) (14), a quantizer (16) which quantizes the input signal en(k) (14) to an output signal yn(k) (18) according to a predetermined quantization function, and a second adder (20) which adds the input signal en(k) (14) with the inverted output signal yn(k) to xn(k) (21), and supplies it to a delay device (22) which sends the signal xn(k) (21) to the first adder (10) as an error signal errn(k−1) with a delay by a clock period. For this purpose, an amount reducer (24) is provided between the second adder (20) and the delay device (22), which amount reducer (24) leaves the signal xn(k) (21) unchanged when xn(k)=0 and otherwise lowers the amount |xn(k)| of the signal xn(k) (21) by at least a smallest representable numerical unit, wherein the quantization function of the quantizer (16) of the nth stage of the sigma-delta D-A converter (300) is expressed as follows: y n ⁡ ( k ) = { 2 ( 1 - n ) , if ⁢   ⁢ e n ⁡ ( k ) > 2 - n 0 , if ⁢   ⁢ abs ⁢   ⁢ ( e n ⁡ ( k ) ) ≤ 2 - n - 2 ( 1 - n ) , if ⁢   ⁢ e n ⁡ ( k )