发明授权
- 专利标题： Jitter correction circuit and a flat panel display device using the same
- 专利标题（中）： 抖动校正电路和使用其的平板显示装置
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申请号： US09006954申请日： 1998-01-14
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公开(公告)号： US06256003B1公开(公告)日： 2001-07-03
- 发明人: Kenshi Tsuchiya , Hirofumi Kato , Hiroyoshi Murata
- 申请人： Kenshi Tsuchiya , Hirofumi Kato , Hiroyoshi Murata
- 优先权： JP9-004902 19970114; JP9-250248 19970916
- 主分类号： G09G336
- IPC分类号： G09G336
摘要：
A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd0 is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd1 through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd1 through Ckdn. The output circuit outputs one of the correction subject signal Ckd0 and the delayed signals Ckd1 trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.
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