A first and second integrated circuit contain respectively a first and second portion of a parallel port, the first portion includes control, configuration, data and status registers and the second portion includes parallel port input and output terminals. A bus couples the first and second integrated circuits and transfers parallel port control and data information between the first and second integrated circuits. The bus includes a clock line providing a clock signal. The bus also includes a data out line that serially transfers output control and data bits from the first to the second integrated circuit, the data and control bits to be provided to the parallel port output terminals on the second integrated circuit. The bus also includes a data in line providing input data and control information from the terminals of the parallel port to the first integrated circuit. The bus provides data either substantially continuously in frames defined by a frame sync or uses a start bit to go from an idle state to a data transfer state according to the read and write operations of the parallel port. The mode of operation of the parallel port determines whether data is transferred continuously in frames or after a start bit.