发明授权
US06265748B1 Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement
失效
垂直MOS晶体管根据存储的数据具有至少三个不同阈值电压的存储单元布置，以及制造所述布置的方法
- 专利标题： Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement
- 专利标题（中）： 垂直MOS晶体管根据存储的数据具有至少三个不同阈值电压的存储单元布置，以及制造所述布置的方法
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申请号： US09180129申请日： 1998-11-02
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公开(公告)号： US06265748B1公开(公告)日： 2001-07-24
- 发明人: Franz Hofmann , Wolfgang Krautschneider , Josef Willer
- 申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
- 优先权： DE19617646 19960502
- 主分类号： H01L2976
- IPC分类号： H01L2976
摘要：
A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).
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