发明授权
US06275905B1 Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system 有权
在多处理计算机系统中的存储器读取操作期间保持高速缓存一致性并节省系统存储器带宽的消息传递方案

  • 专利标题: Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
  • 专利标题(中): 在多处理计算机系统中的存储器读取操作期间保持高速缓存一致性并节省系统存储器带宽的消息传递方案
  • 申请号: US09217649
    申请日: 1998-12-21
  • 公开(公告)号: US06275905B1
    公开(公告)日: 2001-08-14
  • 发明人: James B. KellerDerrick R. Meyer
  • 申请人: James B. KellerDerrick R. Meyer
  • 主分类号: G06F1200
  • IPC分类号: G06F1200
Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
摘要:
In a multiprocessing computer system, a cache-coherent data transfer scheme that also conserves the system memory bandwidth during a memory read operation is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and sending respective probe responses to the source node. Probe command also causes the node having an updated copy of the cache block to send the cache block to the source node through a read response. The target node, concurrently with the probe command, initiates a read response transmission to send the requested data to the source node. The node having the modified cached copy containing the requested data transmits a memory cancel response to the target node concurrently with the updated copy of the cache block to the source node. The memory cancel response attempts to prevent the target node from sending to the source node the stale data from the system memory. The memory cancel response also causes the target node to send a target done response to the source node. The source node waits for probe responses, read responses and the target done message prior to sending a source done message to the target node.
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