A flash memory structure comprises a first polysilicon layer above a semiconductor substrate; a thin dielectric layer above the first polysilicon layer; and a second polysilicon layer across and above the dielectric layer and the substrate, wherein the second polysilicon layer has a linear shape when viewed from the top. The memory structure further comprises a drain region in the semiconductor substrate on one side of the second polysilicon layer; a trench isolation structure for insulating from neighboring devices; a buried metallic layer located inside a portion of the trench isolation structure close to the upper surface of the substrate; and a common source region located on the other side of the first polysilicon layer just opposite the drain region such that the common source region at least includes a source region and a buried metallic layer alternately linked together.