发明授权
US06284593B1 Method for shallow trench isolated, contacted well, vertical MOSFET DRAM
失效
浅沟槽隔离方法，接触良好，垂直MOSFET DRAM
- 专利标题： Method for shallow trench isolated, contacted well, vertical MOSFET DRAM
- 专利标题（中）： 浅沟槽隔离方法，接触良好，垂直MOSFET DRAM
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申请号： US09705652申请日： 2000-11-03
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公开(公告)号： US06284593B1公开(公告)日： 2001-09-04
- 发明人: Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
- 申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
- 主分类号： H01L218242
- IPC分类号： H01L218242
摘要：
A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
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