- 专利标题: Semiconductor device
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申请号: US09761572申请日: 2001-01-18
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公开(公告)号: US06285074B1公开(公告)日: 2001-09-04
- 发明人: Michiaki Sugiyama , Tamaki Wada , Masachika Masuda
- 申请人: Michiaki Sugiyama , Tamaki Wada , Masachika Masuda
- 优先权: JP9-227995 19970825; JP10-46487 19980227
- 主分类号: H01L23495
- IPC分类号: H01L23495
摘要:
In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.
公开/授权文献
- US20010001504A1 Semiconductor device 公开/授权日:2001-05-24
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