发明授权
- 专利标题: Hardware verification tool for multiprocessors
- 专利标题(中): 用于多处理器的硬件验证工具
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申请号: US09304538申请日: 1999-05-04
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公开(公告)号: US06285974B1公开(公告)日: 2001-09-04
- 发明人: Sriram Mandyam , Brian Walter O'Krafka , Ramanathan Raghavan , Robert James Ramirez , Miwako Tokugawa
- 申请人: Sriram Mandyam , Brian Walter O'Krafka , Ramanathan Raghavan , Robert James Ramirez , Miwako Tokugawa
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory. Thereafter, a second sequence of values is read from the memory location and a window of observed values is defined, wherein the window has a highest observable value and a lowest observable value where the highest observable value is set to the highest value of the first sequence and the lowest observable value is set to the lowest value of the first sequence and wherein the lowest observable value is updated with a next observable value from the first sequence whenever the value of an individual read from the second sequence is higher than the lowest observable value so that a determination can be made whether individual values in the second sequence are within the window.
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