A power-up-reset circuit draws zero standby current. Rather than use a voltage divider that always draws current, a capacitive-pullup divider is used as the first stage. The capacitive-pullup divider has a capacitor to power (Vcc) and n-channel series transistors to ground. A sensing node between the capacitor and n-channel series transistors is initially pulled high to Vcc as Vcc is ramped up. The n-channel transistors remain off until Vcc reaches about 1.5 volts. Then the n-channel transistors pull the sensing node quickly to ground, ending the reset pulse. The second stage has a capacitor to ground that initially holds a threshold node low. A p-channel transistor has a gate connected to the sensing node and charges up the capacitor when the sensing node falls to ground. A third stage is triggered to change state as the capacitor is charged up by the p-channel transistor. Then a Schmidt trigger toggles, as do downstream inverter stages. A feedback signal goes low, disabling the gate of a pulldown n-channel transistor in the second stage. This disables a power-to-ground current path.