发明授权
US06294426B1 Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole 有权
在增加电容的位线结构下制造电容器的方法,而不增加干蚀刻位线接触孔的纵横比

  • 专利标题: Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole
  • 专利标题(中): 在增加电容的位线结构下制造电容器的方法,而不增加干蚀刻位线接触孔的纵横比
  • 申请号: US09765041
    申请日: 2001-01-19
  • 公开(公告)号: US06294426B1
    公开(公告)日: 2001-09-25
  • 发明人: Kuo-Chi TuChih-Hsing Yu
  • 申请人: Kuo-Chi TuChih-Hsing Yu
  • 主分类号: H01L218242
  • IPC分类号: H01L218242
Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole
摘要:
A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.
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