发明授权
- 专利标题： Semiconductor device with electrical isolation means
- 专利标题（中）： 具有电隔离装置的半导体器件
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申请号： US09494785申请日： 2000-01-31
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公开(公告)号： US06299314B1公开(公告)日： 2001-10-09
- 发明人: Motoshige Igarashi , Hiroyuki Amishiro , Keiichi Higashitani
- 申请人： Motoshige Igarashi , Hiroyuki Amishiro , Keiichi Higashitani
- 优先权： JP11-218503 19990802
- 主分类号： H01L2976
- IPC分类号： H01L2976
摘要：
Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.