There is provided a memory testing apparatus capable of applying two address signals to a failure analysis memory in one test period, in the case that a memory under test operates in burst mode and adopts double data rate system. There is provided a burst address producing circuit 8 capable of producing two burst address signals in one test period, which comprises a clock-repetition-rate doubling circuit 15 for outputting a clock at twice the pulse repetition rate of the test period signal TI, a first multiplexer 16 for selecting either one of the clock TI and the rate-doubled clock from the circuit 15, and a burst address generating circuit for generating an address signal to be supplied to the failure analysis memory 5. The burst address generating circuit outputs two burst address signals in one test period by computing operation using an address signal first supplied from the pattern generator 2, in the case that a memory under test operates in burst mode and adopts double data rate system, and supplies them to the failure memory as burst address signals.