发明授权
US06316293B1 Method of forming a nand-type flash memory device having a non-stacked gate transistor structure
有权
形成具有非叠层栅极晶体管结构的n型闪存器件的方法
摘要：
A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure (346) containing an interpoly dielectric layer (322) for one or more flash memory cells in a core region (305). The method also includes forming a select gate transistor structure (348) having a first gate oxide (322) formed of the interpoly dielectric material and a gate conductor (338) overlying the first gate oxide (322) in the core region (305). A NAND-type flash memory device includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (348) and a periphery region (314, 315) comprising a low voltage transistor (342) and a high voltage transistor (350). The stacked gate flash memory cell structure (346) includes a tunnel oxide layer (308), a poly1 layer (312) overlying the tunnel oxide layer (308), an interpoly dielectric layer (322) formed of an insulating material overlying the poly1 layer (312) and a poly2 layer (338) overlying the interpoly dielectric layer (322). In addition, the select gate transistor structure (348) includes a gate insulator (322) formed of the insulating material and a poly2 layer (338) overlying the gate insulator (322).
信息查询
