发明授权
US06320127B1 Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
有权
用于减少电子部件封装的底部填充层中的空隙发生率的方法和结构
- 专利标题： Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
- 专利标题（中）： 用于减少电子部件封装的底部填充层中的空隙发生率的方法和结构
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申请号： US09465425申请日： 1999-12-20
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公开(公告)号： US06320127B1公开(公告)日： 2001-11-20
- 发明人: Kumar Nagarajan , Sarathy Rajagopalan
- 申请人： Kumar Nagarajan , Sarathy Rajagopalan
- 主分类号： H05K506
- IPC分类号： H05K506
摘要：
A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.
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