发明授权
- 专利标题： Reducing impact of coupling noise in multi-level bitline architecture
- 专利标题（中）： 减少耦合噪声对多级位线架构的影响
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申请号： US09406890申请日： 1999-09-28
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公开(公告)号： US06327170B1公开(公告)日： 2001-12-04
- 发明人: Gerhard Mueller , Ulrike Gruening
- 申请人： Gerhard Mueller , Ulrike Gruening
- 主分类号： G11C508
- IPC分类号： G11C508
摘要：
An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number≧1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number≠m. The vertical-horizontal twists transform coupling noise into common mode noise.
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