A method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening. A spacer is formed on the sidewalls of the lower electrode opening above the polysilicon layer. Using the spacers as a mask, the polysilicon layer is etched to form a lower electrode with a recess groove above the node contact opening. The second dielectric layer and the spacers are removed. To complete the fabrication of the DRAM cell capacitor, a dielectric layer is formed over the lower electrode and an upper electrode is formed over the dielectric layer.