发明授权
- 专利标题: Capacitor over bit line memory cell and process
- 专利标题(中): 电容器在位线存储器单元和工艺
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申请号: US09526559申请日: 2000-03-16
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公开(公告)号: US06329682B1公开(公告)日: 2001-12-11
- 发明人: Kunal R. Parekh , John K. Zahurak
- 申请人: Kunal R. Parekh , John K. Zahurak
- 主分类号: H01L27108
- IPC分类号: H01L27108
摘要:
A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.
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