发明授权
- 专利标题: Time slot assignment circuit
- 专利标题(中): 时隙分配电路
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申请号: US09150721申请日: 1998-09-10
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公开(公告)号: US06330237B1公开(公告)日: 2001-12-11
- 发明人: Yukio Suda , Satoshi Nemoto , Yasuhiro Murakami , Masahiro Shioda
- 申请人: Yukio Suda , Satoshi Nemoto , Yasuhiro Murakami , Masahiro Shioda
- 优先权: JP10-071843 19980320
- 主分类号: H04L1250
- IPC分类号: H04L1250
摘要:
A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.
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