发明授权
- 专利标题： Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures
- 专利标题（中）： 包括提取单元的装置，包括分支历史信息以增加多流水线分支预测结构的性能
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申请号： US09256623申请日： 1999-02-23
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公开(公告)号： US06330662B1公开(公告)日： 2001-12-11
- 发明人: Sanjay Patel , Adam Talcott , Rajasekhar Cherabuddi
- 申请人： Sanjay Patel , Adam Talcott , Rajasekhar Cherabuddi
- 主分类号： G06F930
- IPC分类号： G06F930
摘要：
An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.
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