发明授权
- 专利标题： Wafer-scale package structure and circuit board attached thereto
- 专利标题（中）： 晶圆尺寸的封装结构和电路板
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申请号： US09353385申请日： 1999-07-15
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公开(公告)号： US06333469B1公开(公告)日： 2001-12-25
- 发明人: Yasushi Inoue , Masakazu Sugimoto , Megumu Nagasawa , Takuji Okeyui , Kei Nakamura
- 申请人： Yasushi Inoue , Masakazu Sugimoto , Megumu Nagasawa , Takuji Okeyui , Kei Nakamura
- 优先权： JP10-202227 19990716
- 主分类号： H05K116
- IPC分类号： H05K116
摘要：
A wafer-scale package structure in which a circuit board for rearranging electrode pads of a wafer is laminated on the wafer integrally. The circuit board can be divided into individual chip-size packages (CSPS) and which includes a layer of polyimide resin, and connection between the wafer and the circuit board is performed by solder bump, while the circuit board is stuck on the wafer with an adhesive.
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