发明授权
- 专利标题: Integrated circuit vertical trench device and method of forming thereof
- 专利标题(中): 集成电路垂直沟槽器件及其形成方法
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申请号: US09597389申请日: 2000-06-19
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公开(公告)号: US06335247B1公开(公告)日: 2002-01-01
- 发明人: Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
- 申请人: Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.