A parallel-serial conversion circuit includes a frequency divider circuit which outputs a dichotomized signal of an input clock signal. A positive edge triggered flip-flop and a negative edge triggered flip-flop receive data and the dichotomized signal is input. A tap signal generator receives the clock signal and generates and outputs a series of tap signals by providing different delays to the clock signal. A selection signal generator receives the tap signals and generates a series of pulse signals having the width equivalent to 1 bit of serial data. An inverter circuit inverts the dichotomized signal. A 10-bit parallel-serial converter receives data from of the flip-flops, a signal of the inverter circuit, and the pulse signals. The 10-bit parallel-serial converter performs parallel to serial conversion based on the input data and signals and outputs the serial data.