发明授权
- 专利标题： Semiconductor memory device and defect remedying method thereof
- 专利标题（中）： 半导体存储器件及其缺陷补救方法
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申请号： US09714268申请日： 2000-11-17
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公开(公告)号： US06335884B1公开(公告)日： 2002-01-01
- 发明人: Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
- 申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
- 优先权： JP63-277132 19881101; JP63-279239 19881107; JP1-14423 19890124; JP1-65840 19890320
- 主分类号： G11C1300
- IPC分类号： G11C1300
摘要：
Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
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